The invention relates to a digitally self-calibrating pipeline analog-to-digital converter.
Analog-to-digital converters (ADCs) are used to quantize electrical signals for digital signal processing. The electrical signals quantized arise from a number of physical phenomenon including, but not limited to, pressure, temperature, acceleration and position. ADCs are used in many engineering realms ranging from consumer products, avionics, medical instrumentation and industrial controls. The advent of powerful digital processing systems has increased the need for high performance ADCs. Two chief parameters summarize the performance of ADCs: the resolution and the sampling rate. The resolution indicates how small of a voltage or current that the ADC can resolve. The sampling rate indicates how fast the electrical inputs can be quantized to digital output words.
In order to increase the performance of systems that use ADCs, there is demand for high-resolution ADCs that operate at high-speed. In addition, the use of increasingly sophisticated digital signal processing (DSP) demands higher performance ADCs to alleviate the amount of analog signal processing that is required. Traditionally, high-resolution, high-speed ADCs relied on expensive hybrid or discrete implementation. Such ADCs are not amendable to low cost manufacturing. The use of monolithic integrated circuit (IC) techniques has been repeatedly demonstrated in the digital and analog circuit domains to be extremely economical for synthesizing electronic systems. Thus, construction of high performance ADCs in low cost, MOS IC processes is paramount for achieving low cost.
Process limitations, however, limit the achievable accuracy because of matching limitations. Typically, component values in ADC algorithms are fundamentally related to each other by ratios of the component values. Thus, ratiometric limitations are fundamental limitations of achievable ADC resolution. In order to achieve precise ratios, high precision component tolerances are required in traditional approaches. This is not compatible with low cost, MOS IC processes. The use of calibration techniques is important to eliminate the need for high precision matching. Self-calibration techniques, which are derived from principles of an ADC algorithm, collectively represent a small set of ADC techniques capable of achieving high resolution without the use of precision matched components or external reference data converters.
Pipeline analog-to-digital converters present advantages compared to flash or successive approximation techniques because potentially high resolution and high speed can be achieved at the same time. A 1-bit per stage design is particularly amenable because each stage is very simple and fast. The primary limitations to the accuracy of a switched-capacitor pipeline ADC are capacitor mismatch, charge injection, finite operational amplifier gain and comparator offset. Conventional 1-bit per stage ADCs, including algorithmic and pipeline ADCs, have removed some of these errors by using extra clock cycles with ratio independent, reference refreshing, error averaging and analog calibration techniques. Although the analog calibration does not require extra clock cycles during normal conversions, a weighted capacitor array is needed for each stage to be calibrated. For pipeline ADCs, where many stages are calibrated, the added complexity and capacitive load is significant.